The present invention relates generally to the testing of integrated circuits. More particularly, the invention relates to scan testing of integrated circuits to determine failed functional blocks and partially scan testing the integrated circuit without the failed functional blocks such that the integrated circuit may be tested and sold at a reduced functionality.
Integrated circuitry on a chip is commonly tested. Scan testing is a common way to test integrated circuits by serially shifting test data into an integrated circuit, and then observing the output of the serial data. This method is very effective to determine whether an entire integrated circuit is functioning properly, and may be packaged and sold. The production chips of an integrated circuit to be sold are checked for manufacturing flaws before being furnished to a customer. Testing may also include applying a test program to the circuitry to determine if the logic on the chip responds as desired to various electrical inputs.
Due to processing improvements, it is possible to include an entire computer system on a chip. What was once a number of complex dedicated chips on a motherboard is now a number of complex blocks in an integrated circuit. The number of transistors in the integrated circuit may number in the tens of millions, or even more. The failure of a single transistor within one of these complex blocks will cause an integrated circuit to fail scan testing. As a result, the chip will be scrapped, resulting in a lower yield of usable chips, as well as higher production costs.
In scan testing, each flip-flop in a design to be tested has two input paths, one a functional path, and the other a test path. Each flip-flop in the integrated circuit (IC) is connected serially through the test path. That is, one flip-flop output is tied to the test input of another single flip-flop. A test program may include one or more scan patterns to be applied to the block of the circuit to be tested. First, data is scanned in through the serial test inputs to initialize all the flip-flops in the design. Then the functional input is used to capture data from the cone of logic in the parallel path. This loads each flip-flop with a new value, which is then shifted serially through the test input again. The process continues for many cycles, and serial data is shifted in through the test inputs, and then captured through the functional outputs. After running many cycles, test coverage increases as many different patterns will be run through the cone of logic in the functional path to each flip-flop. The serial scan chains are observed on the integrated circuit outputs, and if a serial pattern matches the expected result, then the IC is deemed good. A typical test sequence in a scan pattern consists of a scan-in operation, a set of input stimulus, and a scan-out operation. Desired values are loaded into the scan flip-flops. During the implementation of a scan, a circuit design is tested as one entity, and the design flip-flops are interconnected into a single, long shift register, or in other words a scan chain. Values are loaded and/or extracted from the scan flip-flops by serially shifting in and out one bit per clock cycle.
FIG. 1 discloses a block diagram illustrating a prior art functional block arrangement. This arrangement illustrates a typical high-level integration design in which there are a number of major functional blocks, in this case block A, block B and block C. In this arrangement, the functional mode, blocks B and C both depend on block A to function. In integrated circuit 10, the output of block A goes to the input of block B via line 12A and conversely the output from block B goes to the input of block A via line 12B. Similarly, the output of block A goes to block C via line 14A and the output of block C goes to block A via line 14B. In each case, each of the functional blocks A, B and C send and receive data via their respective bus line 16A, 16B and 16C. In this arrangement, blocks B and C both depend on block A to function. However, blocks B and C do not depend on each other to function. Therefore, in such an arrangement, if a failure is detected during testing of block A, the entire integrated circuit 10 must be scrapped because there is no ability to salvage the functionality of the remaining blocks. This is due to the fact that block A affects both block B and block C. The inability to prevent information coming out of block A (which is unreliable) from affecting the logic of blocks B and C makes any properly functioning blocks also unreliable. An example illustrating this concept would be an integrated circuit design where block A is a bus interface to a microprocessor, block B is a fire wire interface, and block C is a USB interface. In short, there is no way in the conventional design to bypass a failed functional block from corrupting valid functional block logic.
The problem with this technique in current applications is that if there is a failure in one section of the integrated circuit (IC) the failing section cannot be prevented from affecting the logic in the rest of the IC. Consequently, it is not possible to prove that the rest of the IC is good silicon, and therefore producing valid logic. There currently are techniques that use partial scan testing of individual functional blocks, but these techniques do not adequately test the interaction between the functional blocks, because the failure of one block will corrupt the logic of any associated blocks. Therefore, the testing of functional blocks individually is not useful since they cannot be tested in logical isolation. It is desired to provide a way to isolate an entire functional block from the rest of the integrated circuit and partially test the integrated circuit even when portions of the IC have failed.